AVE (ASTC AMS Verification Environment)


AVE (ASTC AMS Verification Environment): a Faster, Simpler, Lower Cost Solution for Analog / Mixed Signal IC Design Verification

Chip-level functional verification of complex AMS SoC designs is typically performed in an analog design environment with design-centric tools, vs verification-oriented tools. This poses numerous challenges:

  • Lack of automation of test suites limits the amount and scope of verification of the mixed-signal functionality and connectivity that can be performed within a project schedule.
  • The digital portion of the design (RTL) is developed in a separate digital design environment, and is imported late in the design flow as synthesized gate-level/SDF.  This limits the time to verify analog and digital interactions in the integrated design.
  • Functional coverage tools are digital only, so it is very difficult determine the functional coverage of a mixed-signal design.
  • Inability to identify, implement and report traceability between AMS design specification and implementation.
  • Technology design libraries are often read-only and design-centric, providing limited scope for verification-centric extensions.
  • Digital design is block- or design-view based (i.e. RTL/gate), while analog is cell-view based.

Also, functional chip-level design verification of analog, digital and mixed-signal designs are typically handled differently in different environments, with no single environment to perform all verification of all types of designs in a consistent and predictable manner. A typical AMS SoC design project involves the integration of many analog/digital design blocks at various states of completion, while the top-cell design often starts late and is subject to churn. This inhibits obtaining a consistent stable design for verification until too late before tape out. Analog design environments provide limited scope to select an interim design version for verification. Mismatches between design implementation and verification coverage priorities may occur, resulting in verification road blocks (e.g. power supply incomplete, top-level connectivity not implemented, digital core pin/function mismatch with analog block version etc...)

In addition, simulating mixed-signal designs using full schematics for non-power up functionality is prohibitively slow. Models are used to represent part or all of the analog functionality. Time and effort to create, bring-up and maintain verification models may be significant depending on the number of models required, level of abstraction, etc. Verification models are stored within a design database, and when the design changes, the verification models do not, as a result of different ownership. Read-only technology library cells may not support the models required for verification. The schematic hierarchy represents both functional, parametric and layout information. As a result, schematic hierarchy may be organized in a way that complicates the functional modeling needed to resolve simulation bottlenecks. Reusing analog block verification models can be problematic, as the scope/focus can significantly differ from chip-level verification models.

To solve these challenges, ASTC has developed and successfully applied a verification centric environment and methodology for a number of its lead customers that addresses this design verification challenge: AVE!

ASTC Verification Environment (AVE)

ASTC's AMS Verification Environment (AVE) and methodology solution for automation and high quality chip-level verification of current and future generations of complex AMS SoC designs:

  • Provides a verification environment separate from the design environment
  • Creation of a stable and known verification baseline using design import mechanism
  • Automated requirement/test case tracking and reporting
  • Automated generation and configurability of test case/test bench/modelling artifacts
  • Regression testing of AMS design, through test point monitoring in AMS simulation
  • Enhances and complements standard EDA AMS design verification tools from a variety of popular EDA vendors.













The new AVE Templated Test Bench Generation (TTG) tools allow generation of multiple test bench components and artefacts from a single common source, and improve re-usability between projects. The number and configurations of modules within a chip design can be scaled, with the test bench structure also scaling automatically, to improve re-usability within a single project. Common information which may be used in multiple formats and ways within a project can all be sourced from a single location. Changes during the project lifetime affect one central source, which then causes the update of all dependent artefacts.









AVE technology and methodology has helped a number of leading AMS silicon vendors achieve first silicon-to-production success:

  • Design quality reduced spins from 2.x or 3.x to 1.0/1.x
  • Reduced time to market;  NRE cost to production; time and cost of design to tape out; and EDA costs (faster verification and design closure reduce the time-based cost of EDA licenses by a factor of 2)
  • Faster convergence: of product requirements, spec, and verification plan;  to stable and AMS verification-ready design; and of chip level verification with resolution of design issues
  • Improved project management via metric based verification and tape out schedule planning