Fast Functional Verification of Mixed Analog and Digital SoCs

Fast Functional Verification of Mixed Analog and Digital SoCs with Verilog-DMS Discrete Mixed Signal Solution framework and extensions to Verilog/SystemVerilog.

The AMS SoC verification problem includes twinned trends of size and complexity for AMS SoCs, with both increased IP integration, and increased complexity of analog and digital IP integrated in these SoCs/ASICs. Chip-level verification challenges for large and complex AMS SoC designs include:

  • Speed: very slow continuous analog solver simulations with poor convergence
  • Cost: expensive AMS simulators, high engineering time and schedule costs; complexity such as multiple feedback loops, complex interfaces, and interactions between analog and digital, require very costly and slow AMS simulators
  • Coverage: limited chip level verification, with no automated metrics or regression tests

The ASTC solution: Verilog-DMS for AMS SoC verification

ASTC has developed and applied, with a number of customers, a new methodology and tool technology that addresses this AMS SoC design verification challenge. Highlights include superior test coverage alternative to Verilog-AMS (and Wreal) for chip-level AMS SoC verification; 40x to 200x simulation time improvement; and 3x-4x less cost to license.




















DMS, or Discrete Mixed Signal, is a new methodology for modeling and simulating analog circuits for fast functional simulation and verification of AMS SoCs, with reuse of SoC structural netlists (you verify the SoC level design 'as is'); discrete event models of behavior of analog blocks; discrete electrical signals with multiple channels for the different modeled electrical characteristics; and accurate simulation of interconnects and nets via a discrete time electrical law network equation solver.

VVW, for Verilog Virtual Wires, is a proven ASTC technology library for implementing DMS methodology for fast functional AMS SoC simulation and verification on a Verilog simulator, with an electrical interconnect simulation library extension to Verilog/SystemVerilog and a Kirchhoff voltage/current laws compliant discrete time electrical law network equation solver

Verilog-DMS is a DMS solution for fast functional simulation and verification of AMS SoCs, including methodology and tools for development and test of DMS models of analog IP and test bench architecture, methodology and tools for AMS SoC integration and system tests. ASTC's Verilog-DMS methodology and technology is fast and scalable to meet the performance requirements of complete full-chip functional coverage of AMS SoCs. It supports all major Verilog/SystemVerilog simulators (NC-Sim, VCS and ModelSim) and is interoperable with other modeling methodologies - Verilog AMS behavior models, schematic models, Spice...

DMS modeling advantages include fast, functionally complete, and scalable to meet the performance requirements of comprehensive full-chip functional coverage of AMS SoCs, with accuracy defined to meet target system test requirements. Simple DMS models require relatively low effort to develop and test: 2 - 10 day per model typically) and require only analog circuit conceptual understanding plus Verilog/SystemVerilog knowledge, no detailed analog design expertise required. They are faster to simulate: 40x to 200X faster than Verilog-AMS or schematics (for high frequency switching circuits, Verilog-AMS suffers the same simulation speed limitations as SPICE, compared to fast simulation of equivalent DE models) DMS models are easier to debug and work with all major Verilog/SystemVerilog simulators (NC-Sim, VCS and ModelSim.) Another advantage is lower license cost, compared to Verilog-AMS simulators.

Typical applications of Verilog-DMS include high coverage chip-level functional verification of complex AMS SoC devices, supporting multi-channel baseband/RF; power management ICs; modems, codecs; sensor platforms; transceiver ICs and more.
Benefits extend to mixed schematic/DMS test benches for module/subsystem verification, such as for multi-phase Buck regulators, system-level multi-chip communication verification/validation, and pre-silicon device driver development.

Interconnect Feature Comparison:















ASTC's solution to achieving high assurance and functional coverage chip-level verification of current and future generations of complex AMS SoC designs include Verilog-DMS models for fast behavior simulation of AMS and an environment and tools for automated test bench development and test using VVW tool extensions to Verilog and SystemVerilog. 

Across dozens of design verification cycles, results were successful first silicon and early time to market success.

  • Faster: 40x to 200x
  • Less expensive: 3x to 5x lower EDA license cost
  • Improved NRE: reduced engineering time and schedule cost
  • Quality: increased verification coverage