VVW (Verilog Virtual Wires) Technology

VVW, for high-speed, high-coverage system level functional verification of large mixed-signal SoC designs.

With the continuing trend towards increased complexity and highly configurable, digitally-controlled analog blocks, functional verification coverage for  mixed analog/digital SoCs is a real challenge. This results in a significant risk of post-silicon defects and negative impact on cost and time to production. Low coverage can be a result of excessive simulation times when using Spice or Verilog-AMS to model analog blocks, because very few tests are run. Coverage problems often result from digital models which too crudely approximate the behavior of analog blocks. One attempt at a solution was "Real Valued Modeling" (RVM)  but this has somewhat frustrating limitations, and involves much effort.... 

Now there's something better: Discrete electrical modeling with VVW (Verilog Virtual Wires). High simulation speed, broadly applicable, and easy to use, leading to high coverage, confidence in the design, and lower costs.

VVW  is a PLI-based Verilog extension providing full electrical (voltage and current) connectivity between discrete electrical models. "Real Valued Modeling" supports only voltage or current but not both, requires a design's ports to be modified to enable connectivity between models, and supports only mathematical resolution functions.  VVW discrete electrical modeling supports full modeling and connectivity of both voltage and current, on the same wire, without port modification. VVW provides dynamically configurable voltage and current source components, which may be non-ideal (resistive), with network voltage and current resolution according to Kirchoff's laws. VVW is especially well suited to high frequency analog signals (RF), with support for frequency domain connectivity via multiple channels (parameters) on the same wire (e.g. quadrature and in-phase,) resulting in massive simulation speed increases. VVW connectivity mirrors the existing Verilog structural port-based connectivity, while dynamic connectivity (run-time connection and disconnection of nets) is also available using an analog switch component, trivializing the modeling of analog muxes. Connectivity through VHDL blocks is also supported. Key to VVW's ease of use is network debug capability (providing information on which nodes are on a network, as well as their type and state), and network profiling to help identify analog model communication bottlenecks.

While pure discrete electrical modeling is ideal for the majority of system-level functional verification scenarios, it may in some cases be desirable to substitute specific instances of DE models with Verilog-AMS models or (Spice) schematics. A new VVW feature will soon be available, making this substitution possible, using automatically inserted connect modules on mixed signal (discrete-continuous) nets. Multiple channels (parameters) on wires are still accessible with this approach, in the discrete domain.

VVW is available for Linux 32- and 64-bit platforms, and Cadence NCsim, Synopsys VCS and Mentor Modelsim simulators.